In recent years, high function, high performance and small-size electronic apparatuses have been developed, and along with these developments, there have been increasing demands for small-size, light-weight electronic parts to be used in these apparatuses. For this reason, with respect to a semiconductor device packaging method and wiring materials or wiring parts packaged therein, there have been ever-increasing demands for those having high density, high functions and high performance. In particular, materials having a superior adhesive property, which can be desirably used for high-density packaging materials such as semiconductor packages, COL (chip-on-lead) packages, LOC (lead-on-chip) packages and MCM (Multi Chip Module), printed wiring board materials such as multilayer FPCs, aerospace and aircraft materials and fixing materials for automobile parts are being wanted.
Conventionally, regarding semiconductor packages and other packaging materials, acrylic resin, phenolic resin, epoxy resin and polyimide resin have been known as an adhesive which exhibits superior mechanical properties, heat resistance and insulating property. However, phenolic resin adhesives and epoxy resin adhesives which have a superior adhesiveness have inferior flexibility and acrylic resin adhesives which have superior flexibility have inferior heat resistance.
In order to solve these problems of adhesives, using a polyimide resin has been investigated. Among various organic polymers the polyimide resin is superior in heat resistance and thus used in a wide range of fields from aerospace and aircraft fields to electronic communication fields and also used as an adhesive. However, the polyimide resin adhesive, which has high heat resistance, requires a high temperature of approximately 300° C. and a high pressure in order to adhere and in addition, the adhesion strength is not so high. Moreover, when used for semiconductor package and other packaging materials, imide resin adhesives had problems that regarding solder heat resistance and PCT (pressure cooker test) resistance, swelling occurred after solder packaging process and that the adhesion strength decreased remarkably after the PCT process.
Printed wiring boards having a circuit on the surface are widely used in order to package electronic parts and semiconductor devices. With the recent demand of miniaturization and high functions in electronic equipment, high densification and thinning of circuits are strongly desired in printed wiring boards. Particularly, the establishment of a method of forming microcircuit in which the line/space interval is at most 25 μm/25 μm is an important problem in the printed wiring board field.
A method called the semi-additive process is being considered as a method for preparing such a high density printed wiring board and as an example, the printed wiring board is prepared in the following steps.
After a plating catalyst such as a palladium compound is applied on the surface of an insulating substrate made of polymer material, electroless copper plating is conducted with the plating catalyst as the nucleus and a thin metal coating is formed on the surface of the insulating substrate 1.
A resist coating is applied to the surface of the copper coating formed in the above manner and certain portions of the resist coating where the formation of the circuit is planned are removed. Electroplating of copper is then conducted with the area in which the electrolessly plated coating is exposed as the feeding electrode and a second metal coating is formed thereon to form a circuit.
After the resist coating is removed, electrolessly plated copper coating is removed by etching. At this time, the surface of the electroplated copper coating is also etched in about a thickness of the electrolessly plated copper coating and the thickness and width of the circuit pattern decreases.
Furthermore, nickel plating or gold plating is conducted to the surface of the formed circuit pattern according to need to prepare the printed wiring board.
In the semi-additive process, because the circuit is prepared by applying a circuit pitch based on the resolution of the photosensitive plating resist, a microcircuit can be accurately formed, compared to the process called the subtractive process in which a circuit is formed by etching thick metallic foil.
However, the semi-additive process used for preparing a printed wiring board having a microcircuit is known to have the following problems.
The first problem is the problem of adhesion between the formed circuit electrode and the substrate. As mentioned before, the space between the substrate and the circuit electrode is in electrolessly plated copper layer. The electrolessly plated layer is formed in the presence of a catalyst applied on the surface as the active site and therefore is not essentially considered to be adhesive to the substrate. When the unevenness of the substrate surface is great, the adhesion is favorably maintained by the anchor effect, but as the board surface becomes smooth, naturally, the adhesion tends to become weaker.
Hence, a step for roughening the surface of the polymer material which is the substrate is necessary in the semi-additive process and usually, unevenness of approximately 3 to 5 μm based on Rz value is created. This unevenness on the substrate surface is not a practical problem when the line/space value of the circuit to be formed is at least 30 μm/30 μm. However, the unevenness is a great problem in forming a circuit with a line width of at most 30 μm/30 μm, particularly at most 25 μm/25 μm, as this very thin, high-density circuit line is influenced by the unevenness of the board surface and it becomes difficult to form a circuit having a good shape.
Therefore, in forming a circuit with a line/space value of at most 25 μm/25 μm, the flatness is preferably at most 3 μm, more preferably at most 1 μm on a Rz value basis and good adhesiveness is necessary.
The second problem of the semi-additive process lies in the etching step. The electrolessly plated copper layer used as the feeding layer for electroplating copper layer is a layer unnecessary for the circuit and must be removed by etching after the electroplating copper layer is formed. However, when the etching time for removing the electrolessly plated copper layer is long, though the electrolessly plated copper layer is completely removed and insulating reliability becomes high, the circuit pattern of the electroplated copper layer also decreases in width and thickness and producing an accurate circuit pattern with good reproductivity becomes difficult. On the other hand, when the etching time is short, though a good circuit pattern can be obtained, electrolessly plated copper layer remains in some part and insulating reliability is low. In other words, forming an accurate circuit and ensuring high insulating reliability is not compatible. The thinner the line width and thickness becomes, the more serious the problem.
The third problem is the electric insulation. When the line/space value is at most 25/25 μm, maintaining insulation between the circuits becomes difficult in the conventional material. In order to achieve high insulating property, conducting the etching of the electrolessly plated copper layer completely and using a material having a larger insulation resistance than that of the conventional material is important.
Furthermore, the fourth problem is the dielectric characteristics of the resin material. As the clock frequency of the semiconductor increases, reducing signal delay and transmission loss, that is, low dielectric constant and low dielectric loss tangent in a GHz band are required for the wiring board materials. However, the conventional materials, for example, epoxy resins, have a relative dielectric constant of 3.5 to 4.0 and a dielectric loss tangent of approximately 0.03 to 0.05 and therefore, new resins which have a low dielectric constant and low dielectric loss tangent are in demand.